`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:18:48 01/12/2011 
// Design Name: 
// Module Name:    decode 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module decode#(parameter INST_WIDTH = 16, OP_CODE_WIDTH = 4, LOG_NUM_REGS = 2, IMM_WIDTH = 8)
(
    // Incoming instruction from the Imem
    input [INST_WIDTH - OP_CODE_WIDTH - 1 : 0] inst_in,

    // The encoded register bits (going to the register file)
    output [LOG_NUM_REGS - 1 : 0] r1_out,
    output [LOG_NUM_REGS - 1 : 0] r2_out,

    // The immediate (possibly ending up at the register file)
    output [IMM_WIDTH - 1 : 0] imm_out   
);

	always @(*)
		begin
				
		//inst_in[11:10]
		r1_out = inst_in[INST_WIDTH - OP_CODE_WIDTH - 1: INST_WIDTH - OP_CODE_WIDTH -LOG_NUM_REGS ];
		//inst_in[9:8]
		r2_out = inst_in[INST_WIDTH - OP_CODE_WIDTH - LOG_NUM_REGS -1: INST_WIDTH - OP_CODE_WIDTH -LOG_NUM_REGS - LOG_NUM_REGS];
		//inst_in[7:0]
		imm_out = inst_in[INST_WIDTH - OP_CODE_WIDTH -LOG_NUM_REGS - LOG_NUM_REGS -1:0];
	end

endmodule
